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FPGA标准接口卡规范_VITA57DOT1

FPGA标准接口卡(FMC)的规范

ANSI/VITA 57.1-2008 - Revisions Under Consideration The VITA 57.1 working group is considering the following changes to ANSI/VITA 57.1-2008 that would affect compliance and interoperability. NOTE: This

information is provided for information only. While the working group is currently considering these changes, they may or may not be approved by the working group and may or may not become part of a revised standard. Contact VITA for more information. October 2008.

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nChange of CLK*_C2M to CLK*_M2C

Version 1.0 of the standard has defined clocks signals from the carrier card to the mezzanine card; CLK0_C2M_N, CLK0_C2M_P, CLK1_C2M_N, CLK1_C2M_P. It is proposed that these signals will now be redefined as additional ‘M2C’ signals.

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A rule will also be added to state that the CLK*_M2C signals need to be populated starting at the lowest ordinal and working up

Application Specific Signal

A permission will be added to allow application specific signals to be added to the upper unused signals pins of the LA,HA and HB banks. However they will still need to meet the voltage rules for those banks.

AC coupling to be placed on the mezzanine card

All AC coupling for the DP signals will all be placed on the mezzanine card. No AC coupling will be placed on the carrier card. Original Signal Label (Version 1.0) CLK0_M2C_P CLK0_M2C_N CLK1_M2C_P CLK1_M2C_N CLK0_C2M_P CLK0_C2M_N CLK1_C2M_P CLK1_C2M_N New Signal Label (Version 1.1) CLK0_M2C_P CLK0_M2C_N CLK2_M2C_P CLK2_M2C_N CLK1_M2C_P CLK1_M2C_N CLK3_M2C_P CLK3_M2C_N Only

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